SR. ASIC DESIGN ENGINEER: RDF201047; CDMA; VHDL

SUMMARY: We have an ASIC Design Engineer position that has opened up in our Santa Clara office. This person will be reporting to a supervisor that is located in NC, so they should be comfortable with this. Also, the candidate will be responsible for supporting teams in Santa Clara as well as San Diego so they should have the flexibility of possibly traveling to San Diego if needed to. Employee will assist Company design teams in migrating to new "Design Management" methodology. This will include migrating data from legacy system to internal tool, setting up new tool flows for Spyglass, Synthesis, Simulation, RTL to Gate equivalence checking, and ATPG. Employee will work with tool specific support teams to enable the design team in this new methodology.REQUIREMENTS: BS or MSEE with 7+ years related ASIC Design experiences. TOOLS AND LANGUAGES EXPERIENCES: DesignSync Perl scripting Verilog language VHDL language TCL scripting DesignCompiler Conformal equivalence checking Modelsim simulation Vera language Tetramax Spyglass lint checking PrimeTime ***Seeking Local, Bay Area Candidates to work in Santa Clara for this 6 month W-2 Contract***Email your resumePlease click here,or copy and paste the following link into your email browser, to email your resume. SanJoseCAPro.21990.479@manpowerna.aplitrak.com At Manpower, our mission is to serve as trusted advisors in the changing world of work. Work with us and make a change for the better. us.manpower.com manpowerprofessional.com