Sr. MTS Design Engineer (logic) MA3478

Experienced ASIC logic design engineer needed for Vitesse with their cutting edge full custom chip development team in Westford, Mass.  The candidate will participate in definition, specification, RTL implementation and unit testing for large-scale chip design projects.  Responsibilities include determining verification requirements and constraints generation for static timing and synthesis. The individual will be working with a design that includes custom logic, high-speed I/O, Vitesse IP, and large logic blocks with memories. Responsibilities include floor planning, linting, constraints generation, RTL synthesis and static timing analysis. The individual will be responsible for interfacing with the verification and back-end design teams definition through tape-out. Must be able to work independently and engage in technical dialog with customers and peers.  Knowledge of the issues associated with complex ASIC designs is required, including logic synthesis, functional verification, constraints generation, and timing driven design techniques.  The candidate must be fluent in either Verilog or VHDL.  Knowledge of the following tools is desired: Modelsim Questa, PrimeTime, HDLscore, Magma Blast RTL, Mentor BSD Architect, and Fastscan.  Knowledge of OTN, SONET and Ethernet protocols is preferred.  BSEE or MSEE with 5+ years of industry experience in ASIC design.  Vitesse Semiconductor offers a competitive salary and immediate, comprehensive benefits package. We are an equal opportunity employer M/F/D/V.