STA/DFT/Synthesis Lead / 08-09325

Position Description:Leading the charge in next generation enterprise servers is Broadcom’s NetXtreme II family of converged network interface controllers (or C-NICs) designed to drastically change the way servers are built and deployed in the future. Broadcom's Ethernet Controllers offer the widest range of products in the industry. Join a team of highly competent ASIC designers involved in design, verification, and implementation (ASIC) of network controllers in the server segment working on emerging technologies like TCP offload, iSCSI etc.You will have primary Responsibilities for:DFT/Timing closure/Prototyping Engineer to perform any of the following ASIC tape-out tasks:- Generate and maintain RTL, synthesis and layout guidelines for Scan, BIST and Boundary Scan.- Perform scan insertion and generate ATPG vectors.- Debug ATPG vectors on tester.- Prototyping for early area, timing and/or routing estimation and bottleneck analysis.- Setup Lint rules to catch Synthesis/DFT issues.- Timing/crosstalk design closure.- Static Timing/Noise/Coupling Analysis.Responsibilities will also include:- Implementing tool flows and developing CAD methodologies, generating flows & scripts.- Evaluation of tools in the development of new tool flows.- Responsible for day to day DFT/prototyping/timing closure issues in meeting project schedules.Qualifications:The following are essential skills:- ASIC design & implementation experience with specific background in the areas of timing closure, DFT, tool flow methodology.- Minimum 10 years of experience with BSEE or 7 years with MSEE- Hands on experience with any of the following DFT, static timing and crosstalk analysis, early design prototyping for layout & timing closure.- LogicBist, MemBist, Boundary Scan experience a plus.- Understanding of synthesis/timing closure concepts.- Understanding of static timing and crosstalk/noise analysis.- Write and read RTL in Verilog and/or VHDL.- Coding in scripting languages such as TCL, Perl and UNIX shell.- Ability to write/read block and chip engineering specifications.- Hands on experience with following layout CAD tools (the “*� indicates the preferred tools): • DFT: DFT Compiler, DFT MAX, LogicVision*, TetraMAX*. • Lint: Spyglass*. • Synthesis: Design Compiler*, BlastRTL. • Static timing: Primetime*, Magma*, Hspice. • Noise analysis: Celtic*, Primetime-SI.