Reliability Senior Engineer

Position Description:

Purpose of this Group:Ensure all of Spansion’s new technologies have been designed to surpass all reliability spec requirements from the first stage of technology definition and design to the final stage of manufacture and production. TRE works toward identifying new reliability hazards for each developing technology and designing proper test structures and methodologies to avoid these hazards. This requires development of proper lifetime model for performance degradation and failure mechanisms in devices and circuitry by thorough understanding of failure mechanism in a silicon chip, such as gate oxide degradation and integrity, interlayer dielectric failures, and electromigration phenomena. TRE also develops, implements, and transfers wafer level reliability (WLR) methodologies to each fabrication facility to monitor wafer manufacturing to achieve world class reliability. We support the design of reliable products by identifying, developing, and updating technology reliability design rules, tools, and procedures. We aim toward improving all reliability aspects of device and circuit design, process design, and manufacturability of Spansion’s products. Therefore, TRE is in the critical path of ensuring that Spansion's products will succeed in the market place and deliver added value to our customersJob Description:1. Develops key reliability test methodologies in the FEOL (e.g., TDDB, NBTI), BEOL area (EM, SM (stress migration)), BTS (biased temperature stress), ILD-VRDB (voltage ramp dielectric breakdown), isothermal test) and models the degradation mechanisms.2. Co-ordinates with Integration and Process Development to ensure that the device reliability meets our criteria. 3. Develops reliability related electrical design rules.4. Designs and implements required reliability test structures on TCs and SLMs.5. Develops and executes the Qualification plansincluding the reliability testing, extrapolating lifetimes and writing Qual reports.6. Coordinates with the Fab to ensure successful technology qualification within the required timelines. 7. Analyze impact of process variation, realiability margin and stress-induced noise in single and memory arrays.8. Develop a framework for reliability analysis for CAD tool and eventually propose a design methodology for CMOS circuits.

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Qualifications:

PREFERRED EDUCATION AND EXPERIENCE:1. Prefer experience with design tools such as HSPICE, Cadence, Xilinx, Synopsis Design Compiler2. Experience with C/C++, HTML/Verilog3. Ph.D. or M.S. in EE, Physics or related discipline. 4. Knowledge in programming test set-ups, modeling device performance is a plus.