Principal Digital High Speed Design Engineer (3252)

Description

The candidate is a principal level engineer specializing in high speed board schematics design.

The candidate should have experience with Cadence Concept HDL schematics capture tool and familiar with the Cadence Allegro board layout tool. Schematics duties includes but not limited to schematics capture, design error check, generate BOMs, write ECR, and write board description document.

The candidate should be familiar with Ethernet and Fibre channel technologies, copper and fiber interfaces.

The candidate should be familiar with switching power supply design used in DC-DC converters.

The candidate should understand board level EMC/EMI issues, related to placement and routing and make recommendations to improve the quality of the design.

The candidate should be able to establish design reviews, mitigate the risk and recommend solutions.

The candidate is required to interface with different functional groups in the company such as Layout, SI, Purchasing and Manufacturing and HW DVT.

The candidate should be able to multitask.Required SkillsBachelor's degree in Engineering and a minimum of 10 years of high speed signaling experience. Incumbents must possess proven analytical ability and a high level technical background to perform complex research and development work. Technical leadership ability required