Power Management IC Design Engineers, Sr. - Chandler, AZ

Job Description
QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.

QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.

QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.

New Chandler AZ Design Center

Apply your analog integrated circuit design expertise to the development of power management integrated circuits for portable battery powered wireless and consumer electronics applications. These devices contain low drop out linear voltage regulators, step up and step down switch mode voltage regulators, battery charge controllers, crystal oscillators, precision references, comparators, audio amplifiers, video amplifiers, precision current sources and high speed data transceivers

Skills/Experience
Requires previous experience with circuit types listed above. Experience with multiple voltage domain design techniques is essential. Strength in device physics and ultra low power design techniques is a plus. Good lab skills are also essential.

Requires 4-10 years analog transistor-level design industry experience. (BiCMOS, bipolar, CMOS)as well as a knowledge of Cadence or other analog IC design tools.

Additional Skills

Education Requirements
Requires BSEE. MSEE preferred.

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