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 Physical Layer Hardware Logic Design Engineer (Palo Alto, CA)

Details
Country: USA
Location: California-Silicon Valley/Peninsula Palo Alto, CA 94301
Total applied: 40
Job Category:Engineering
Location:Palo Alto, CA 94301
Status:Full Time, Employee
Occupations:Electrical/Electronics Engineering
Career Level:Experienced (Non-Manager)
Physical Layer Hardware Logic Design Engineer (Palo Alto, CA)

Job Description
As a senior Physical layer hardware logic design engineer, you will be primarily working on implementation of physical layer digital signal processing algorithms for wireless local area networking applications. You will be working with the algorithms and C fixed point implementation teams to understand the algorithm and evaluate the hardware impacts; suggest modifications with ASIC constraints in perspective.
In addition to these collaborative activities, you will be responsible for converting the fixed-point models in C into logic design with Verilog as the primary hardware description language. You will be responsible for working with the verification engineers to develop a unit-level and integrated-level testbenches. Using these platforms, you will be responsible for debugging your designs in stand-alone mode and also when integrated with the rest of the chip. You will also be responsible for synthesis and gate-level timing analysis tasks related to your module and to assist with verification and timing of the entire chip.

In addition, you will be responsible for developing project schedules and for tracking the progress of your team to meet the agreed-upon milestone dates. You will provide leadership for small teams of engineers for your section of the ASIC and will be the first point of contact for to the other faculties in the engineering department for any matters related to your section of the chip.


Skills/Experience
. Knowledge of digital signal processing techniques, preferably in the areas of 802.11 PHY or OFDM
. Experience with fixed point design and implementation
. Several years experience with Verilog ASIC design
. Experience with RTL verification
. Experience of Synopsys ASIC synthesis and gate-level timing


Additional Skills
. Experience with Matlab, C++ preferred
. Experience of FPGA synthesis and emulation preferred
. Experience with developing and tracking project schedules
. Good verbal and written communication skills
. Good people skills/Team builder


Education Requirements
Required: Bachelor's, Electrical Engineering
BS/MS Electrical Engineering


$

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