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Home Electronics, Components, and Semiconductor Mfg MEMS-Array-Design-System-Engineer


 MEMS Array Design & System Engineer

Details
Country: USA
Location: California-Silicon Valley/San Jose San Jose, CA 95101
Total applied: 40
Job Category:IT/Software Development
Location:San Jose, CA 95101
Status:Full Time, Employee
Occupations:Systems Analysis - IT
Career Level:Experienced (Non-Manager)
MEMS Array Design & System Engineer

Job Description
The successful candidate will be a key member of the team developing display modules based on the QMT Mirasol display technology. Mirasol displays, based on MEMS technology, offer significant benefits for portable electronic devices, including very low power consumption, excellent readability and robust operation, and will enable new generations of portable devices with increased functionality.

As member of a dynamic team, with high visibility, successful candidate will be involved
in system level design activity from concept to product. Responsibilities include:

. Leading/contributing design of MEMS array to meet product-requirements in collaboration with cross-functional and multi-disciplinary teams within QMT.
. Performing system level electro-mechanical simulations and building behavioral models (using tools such as Ultra-sim, VerilogA, Convetor, and so on) to define analog requirements for driver, system budgets, array performance and connectivity.
. Involvement with display characterization to verify electro-mechanical-optical performance of the pixel array.


Skills/Experience
Qualified candidates will have 3-5 years of array design experience for display or sensor applications with hands on experience on using SPICE modeling/simulation tools. Working experience in multi-disciplinary environment, familiarity for design flow and fabrication process, exposure to device modeling, background in characterization, and experience with MEMS technology are plus.

Specific requirements include:
. System level hands-on design experience in a mixed-mode environment
. Experience with design & verification in a Cadence analog design environment (ADE) with experience on using Verilog-A language
. Strong device physics, simulation, and measurement background are plus


Additional Skills
1)Strong analytical, problem-solving and detail oriented skills.
2) Strong communication, documentation and presentation skills.
3)Eagerness to learn and willingness to take on challenges.


Education Requirements
Minimum of a Bachelors' degree in Electrical Engineering, Physical Science or related field of study required PLUS 10+ years of applicable academic or industry experience.

$

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