Digital Verification Engineer

Digital Verification Engineer

Required Skills Capable of verifying large, DSP centric designs. Capable of verifying designs with embedded CPU's and sizeable firmware and host side software. Has worked with at least one design in excess of one million placeable instances. Experienced with Verilog, SystemVerilog, and C. Willingness to work in small teams (possibly as small as one) and willingness to contribute in all aspects of the design cycle if and when necessary. Willingness to work with design engineers to build up conceptual understanding and to identify portions of designs that are not adequately tested. Willingness to gather and iteratively improve code coverage. Experienced with gate level, annotated simulation environments. Experienced with SystemC and Testbuilder.

Desired Skills Experience with Spyglass and Cadence tools preferred. Knowledge in DSP algorithm preferred, NTSC, DVB-T, MPEG. Strong Perl skills. Knowledge in FPGA implementation, Chipscope, FPGA prototyping or Hardi.

Education and Work Experience

BSEE or MSEE (preferred) +3 years experience.