DFT Methodology and Flow EDA Engineer

Job Description: Individual contributor or project lead to design and implement various DFT Tool flows and methodologies including: Memory BIST, Scan Test, JTAG, Analog/rf/High-speed-I/O Testing from Design through tape-out and support of debug and ATE for manufacturing.  DFT metrics for the DFT Methods include: Test Cost (area and time on tester), Quality (DPPM) and time-to-implementation of DFT Design.

 

Skills/Experience: Direct experience in DFT flow development using various hardware compressors including but not limited to Xor or MISR based compression schemes also to include at speed DFT methods.

DFT (Scan, MemoryBIST, JTAG,Test compression, Logic BIST). Also ASIC RTL and gate design, Verification, synthesis, and timing analysis are desirable. Tool experience: All DFT suppliers' DFT tools, Also synthesis and timing tools and physical design tools. Language Experience with most of the following is highly desirable: VHDL, Verilog, Unix, Scripting languages, C/C++.

 

Education Requirements: Bachelor's degree and six years of experience, a Master's degree and four years of experience or a PhD and two years of experience (or greater).

 

Contact: John Visconti at jv@cae-jobs.com   or 978-667-6680

CAE Recruiters http://www.cae-jobs.com

25 years experience in design automation careers.

All inquiries are held in the strictest confidence.