ASIC SOC Lead

MINDSPEED TECHNOLOGIES, INC. Headquartered in Newport Beach, California. The company's three key product families include high-performance analog transmission and switching solutions, multiservice access products designed to support VoIP and data services across wireline and wireless networks, and WAN communications solutions including T/E carrier, network processing and traffic management devices. Mindspeed's products are used in a wide variety of network infrastructure equipment including voice and media gateways, high-speed routers, switches, access multiplexers, cross-connect systems, add-drop multiplexers and digital loop carrier equipment. We offer a competitive salary, and a comprehensive total benefit package. Mindspeed is a global, equal opportunity employer who supports diversity in the workplace.

Position Description:

The SOC team lead will remotely manage and build an experience and motivated ASIC design and verification team based on Mindspeed’s Dubai Design Center. The role involves working with cross functional teams on existing and new product development.Typical responsibilities/duties include the following:Work with Marketing and Systems Engineering in defining new products architecture.Developing micro-architecture specification for an entire ASIC as well as detailed design documentsPerform feasibility analysis on new chip design. This usually include estimate for area, power consumptions, and cost.Create detailed development plan for an entire ASIC. This includes number and type of resources needed.Work with physical design team to bring tapeout to closure.Evaluate and analyze issues with existing products.

To Apply Visit Mindspeed Technologies, Inc.

Qualifications:

EE Degree, BS with 10+ years of experience, MS preferred.Strong ASIC design and verification experience including:led a team through entire ASIC design cycle from spec to production silicon on at least one programsignificant experience with lab debug and device characterizationdemonstrable knowledge of the Verilog language plus front-end synthesis (Design Compiler) and static timing (Prime Time) toolsexperience developing micro-architecture specifications for an entire ASIC or large blocksKnowledge of ASIC physical design process including: floor planning, place & route, pad ring and package design, power distribution & analysis, thermal analysis, and DFTBoard design experience is highly desired:designed and debugged at least one board-level productknowledgeable about board-level power distribution, device decoupling, signal integrity, transmission-lines and termination issuesExperience with customer support and legacy productsLeadership personality, ability to mentor and motivate team members, and good planning skills.