ASIC Design RTL C C++ Verilog VHDL EDA NCim Primetime Broadband

ASIC Engineer Responsible for design, RTL coding, simulation and synthesis of intellectual property blocks used in ASIC designs. Working knowledge of design principles and practices as well as high level language coding is required. Knowledge of EDA tools for simulation and synthesis is desirable. 5-10 years industry experience required with BSEE. Minimum 2 years of Verilog or VHDL, C or C++ programming. Preferred Experience includes: simulation or synthesis background; EDA Tools – NCsim, DC Shell, Primetime etc. Excellent relo pkg and benefits for these permanent ASIC positions.Email Resume and Salary to connect with our technology client in Southeast. IPCJOBS@knology.net INDEPENDENT PERSONNELTom Thrailkill, President"Technical & Executive Recruiters"256-883-6511 * 256-468-8652 (cell)