Senior ASIC/Timing Engineer

Visualize your future . . . We DoNVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold. SENIOR ASIC/TIMING ENGINEER #1121350

As a senior member of our ASIC team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as clocks/timing/convergence/design for test and scripting of flows. Specifically you'll be focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic Responsibilities:Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level. Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc. Chip level Integration Develop flow to physically partition and floorplan the entire chip. Develop tcl and dc-shell scripts for performing ECO's. Chip bringup. AC timing characterization and performance tuning in the lab for the memory interfaces, etc Minimum Requirements:BS or MS in Electrical Engineering or Computer Science 7 - 10 years of relevant ASIC design experience ideally with a focus in timing EOE

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