ASIC-Design-RTL-C-C-Verilog-VHDL-EDA-NCim-Primetime-Broadband

ASIC Design RTL C C++ Verilog VHDL EDA NCim Primetime Broadband

ASIC Engineer Responsible for design, RTL coding, simulation and synthesis of intellectual property blocks used in ASIC designs. Working knowledge of design principles and practices as well as high level language coding is required. Knowledge of EDA tools for simulation and synthesis is desirable. 5...

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